The present invention relates in general to semiconductor devices and more specifically to high voltage lateral-diffused-metal-oxide-semiconductor (LDMOS) transistors.
Many applications use switching transistors in their power supplies in order to increase efficiency. These applications often require that the switching transistors withstand high breakdown voltages and operate at a low on-resistance. LDMOS transistors are used in these applications, because they can operate with a high efficiency and their planar structure allows for easy integration on a semiconductor die with other circuitry.
To improve capacity, power-switching transistors typically are formed with multiple interdigitated source and drain regions connected in parallel. To avoid routing high voltage metal over an underlying low voltage semiconductor region, the multiple drain regions are extended to form a common region for disposing a drain-bonding pad. As a result, the surface topography of a LDMOS transistor is typically configured using interdigitated source fingers and drain fingers with tips at the ends of the fingers.
One problem that limits the breakdown voltage of the LDMOS transistor is the concentration of the electric field at the tip of both the source fingers and the drain fingers. Rounding the source and drain tips are used to reduce the concentration of the electric field.
However, rounding the source and drain tips are not adequate at a higher voltage or when a smaller tip is needed, because a higher voltage or a smaller tip further increases the concentration of the electric field at the tip. Previous transistors use rounded tips with a relatively large radius to reduce these electric fields. However, the large radius increases the die size and manufacturing cost of the device, while reducing the radius reduces the breakdown voltage.
Hence, there is a need for a LDMOS transistor that can withstand higher breakdown voltages without increasing the die size and manufacturing cost of the transistor.